Jonathan Sherred
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Professional Objectives

Develop algorithms and CAD tools to aid custom and semi-custom integrated circuit design, mask design, and electrical analysis.

Proficiencies

Digital and analog CMOS circuit design, phase-lock and delay-lock loops, clock and power distribution, and physical design of microprocessors. Development of VLSI design methods, algorithms and software tools (Perl and C). Management of complex projects and diverse personalities.

 

Experience

Independent IC CAD contractor since 1997 doing business as Sound Layers,  Campbell CA

Advance Micro Devices California Microprocessor Design Group

(1999-2001) Consultant. Checking electromigration robustness of K8. Interact with technology development to determine ways to take advantage of EM characteristics. Develop in-house scripts and algorithms, propose and check enhancements to point tools from third party (Simplex), apply the overall flow to check K8 designs. By working with circuit designers and third party CAD developers, assure quality of K8 design.

(1997-1999) Consultant. Worked closely with engineers at Epic (now Synopsys) and AMD to debug Railmill product for power supply checking, developed algorithms and tools for signal electromigration flow of which Railmill was one stage, found many bugs and proposed key enhancements which greatly improved Railmill's accuracy and speed. Architected software system for static (assumption-based rather then simulation-based) analysis of signal electromigration, implemented and applied both assumption-based and simulation-based electromigration checks for K6.

Quantum Effect Design

(1997) Consultant. Incorporated Cooper and Chyan (now Cadence) IC Craftsman router into the microprocessor design flow. Also, debug and clean-up of legacy Cadence Skill code.

HAL Computer Systems, Microprocessor Design Group, Campbell CA

(1995-1996) Engineering Manager of Physical and Electrical Tools. Directed a team of senior engineers providing physical design process, tools, and expertise for the microprocessor division. Trained key physical designers and directed the concurrent physical design of several semi-custom C4 chips. Created and maintained in-house design tools (power and clock distribution, netlist partitioning, regional and global place and route, chip floorplanning and assembly) and analysis tools (RC extraction from layout, post-routing timing analysis, electromigration, power supply IR checks, clock skew, and thermal analysis). As the appointed tapeout gatekeeper, owned physical tapeout checklist, backend tools, and version controls to guarantee efficient, trouble-free and repeatable tapeouts. Also contributed to physical design and IO circuit design of the mesh (crossbar) chip.

(1994) Team Leader for Global Physical Design. With a team of 4 engineers, lead the physical design of CPU, CACHE and MMU chips. Lead related tool developments including chip-level post-layout power and clock checks which greatly enhanced tapeout confidence. Continued to personally own clock distribution circuitry for CPU, CACHE and MMU.

(1992-1993) Senior Design Engineer on HAL's first microprocessor, 64-bit 4-issue SPARC which was presented at ISSCC 1994. Designed, implemented, and checked on-chip clock distribution. Owned all top level physical features and wrote physical design software which became the standard for all bumped ("C4") chips. Played a very significant role in building the first physical design strategy and tool set.

Digital Equipment Corporation, Semiconductor Engineering Group,  Hudson MA

(1992) Senior Engineer. System definition and design of clocking system with low power features for 21066 'Low-Cost Alpha CPU.' System would phase-lock to clock on PCI bus and synthesize internal clock with up to 8 times frequency of the PCI clock. This design minimized microprocessor power by dynamic reduction of clock frequency during processor inactivity.

(1991) Received recognition award as Project Lead for phase-lock-loop (PLL) and signal integrity test chip. Wrote proposal, received support, taped out in 8 weeks. Programmable to emulate noise features of chips such as the 200MHz Alpha processor, this chip enabled characterization of a PLL in the presence of noise. The chip also provided a means to evaluate signal integrity properties of packages. Lead a small design team and worked with the test engineer to screen the parts.

(1989-1990) Circuit design of graphics processor chips and a VAX microprocessor. SRAM design, self-timed SRAM design, optimization of critical timing paths through device size and topology changes. Converted old designs to new manufacturing processes.

(1989) Circuit design of a high-speed, high-precision charge pump for FDDI R&D project. Used feedback techniques to accurately balance UP and DOWN current pulses to minimize steady-state phase error and data reception errors.

(1988) Analog circuit modelling. Developed efficient yet accurate model for simulating a PLL in a noisy environment. Reduced simulation time from weeks to minutes by writing special purpose SPICE models in C. The power supply noise injection was modelled by transfer functions with non-linear gain. By applying measured supply waveforms, the simulation explained the observed problems of a video digital to analog converter (VDAC) chip.

(1985, 1986) Engineering internship in semiconductor design teams.

Massachusetts Institute of Technology

(Spring 1988) Graduate Teaching Assistant for Introduction to Digital Design. Taught recitations, graded assignments, helped define and mentor final projects.

(1986 - 1987) Undergraduate Lab TA for Introduction to Digital Design.

 

Education

Massachusetts Institute of Technology, M.S.EE and B.S.EE 1988

Masters thesis on 'PLL Clock Generator Design' supervised by H.S.Lee. CMOS circuit design was done cooperatively at MIT and Digital Equipment Corporation. After fabrication through MOSIS, chips produced 100MHz clocks from 25MHz input. Design included low noise differential VCO and zero delay clock buffers.

Courses included Analog MOS, Feedback Systems, Advanced Analog Techniques, Introduction to VLSI, Digital Signal Processing, Device Modelling, Device Physics, Musical Acoustics (where I built a very low-frequency clarinet!), Music Composition, and fundamentals of electrical engineering.

 

Personal Profile

Attended White Station High School in Memphis, TN. where I was involved with theatre and music. Received awards for math, music and law as Mock Trial State Champion.

Enjoy playing oboe, acoustic guitar and electric bass as well as singing and writing music. To support community music, I host acoustic music nights at a coffee shop.

Interested in solving the technical and logistics problems of live sound such as automatic feedback control, personalized local sound fields, sound cancellation, automated sound system control, 3D audio imaging for virtual reality, acoustic modelling of rooms and objects.

Love spending quality time with my 5-year-old son who is with me half time.

References available by request